1. Field of the Invention
This invention relates to semiconductor integrated circuits and more specifically relates to quantifying the effect of plasma etching on, and during the formation of, MOS devices.
2. Brief Description of the Prior Art
During the manufacture of an integrated circuit, layers of material are formed by deposition on a substrate and then etchants are used to remove unwanted portions of each layer. The material layers may be deposited by sputtering, evaporation or growth, and the etchant may be a liquid or a plasma. Typically, the deposition and etch steps are selectively repeated successively to form transistors, interconnections, and other selected components of the integrated circuit. While a layer is being etched, an underlying, previously deposited layer may be damaged or otherwise deleteriously affected.
An MOS transistor, formed as described above, may comprise a thin gate oxide separating and insulating a conductive gate from a semiconductive channel region. Damage to the gate oxide layer during plasma etch of the gate may cause a voltage breakdown in the gate oxide when the MOS transistor is operated. Several techniques have been used to attempt to detect damage to oxide layers using devices such as Schottky barriers, capacitors and transistors. However, none of these techniques directly addresses detection of damage to the oxide at the periphery of a MOS transistor gate.
The primary damage caused by etching a conductive layer to form the gate is usually weakened gate dielectric at the periphery of the gate, oxide thinning over wider areas of the gate oxide beyond the periphery of the gate, and "trenching" of the gate oxide at the periphery of the gate or in areas beyond the periphery of the gate. Microtrenches are formed when the etching process removes all of the oxide from a small area or "punches through" the oxide to expose the silicon substrate. The process engineer is interested in detecting and minimizing damage to the gate oxide in order to improve reliability and performance of the MOS device.
Currently, the process engineer has limited means to detect damage to gate oxide layers, such as (a) breakdown measurements on blanket wafers (unpatterned wafers) to detect damage to the oxide layer resulting from general exposure to the etchant, (b) optical photometry measurements of surface index of refraction to detect damage to the oxide layer in patterned wafers, and (c) electron microscopy (SEM/TEM) cross sections to visually determine trenching. Breakdown measurements on a blanket wafer determine if damage to the oxide has occurred anywhere on the wafer, but does not specifically evaluate damage around the edges of an etched structure. Photometry measures the surface index of refraction, and damage to the oxide layer may be inferred from the results, but areas between device structures cannot be adequately resolved. Electron microscopy requires cross-sectioning the integrated circuit, so only damage to the oxide located along the cross-section will be detected. These techniques provide, at best, rough damage estimates and are inadequate for evaluating advanced small geometry processes due to a general lack of sensitivity and an inability to resolve areas between tightly spaced devices, in the case of photometry. Additionally, they are of little use for monitoring a production process since they require special test wafers or rely on destructive testing of a wafer.
It is accordingly a goal of the present invention to provide a means for detecting damage to gate oxide due to plasma etching that is applicable to the evaluation of new processes for forming small geometry integrated circuits as well as to processes which are currently being used for production of integrated circuits.
Other goals and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.